The present disclosure relates to a solid-state imaging device.
In recent years, it is common to use a solid-state imaging device to electronically capture and store an image. The solid-state imaging device is typically called an “image sensor.” The solid-state imaging device is categorized into two major types which are a CCD sensor (hereinafter simply referred to as a “CCD”) and a MOS sensor or a CMOS sensor (hereinafter collectively referred to as a “CMOS sensor”). Such solid-state imaging devices each include a minute part (called a “pixel”) configured to output an electrical signal corresponding to the intensity of incident light, and a plurality of pixels are arranged in a matrix, i.e., in rows and columns.
Needless to say, a signal output from each pixel is an analog signal. However, since, e.g., an electronic still camera to which the solid-state imaging device is applied requires a digital signal, conversion of an analog signal to a digital signal, i.e., AD conversion, is required.
Conventionally, it has been often the case that an analog signal is, for AD conversion thereof, output from a solid-state imaging device to outside. However, in such a case, there are the following disadvantages: noise is superimposed on an analog signal outside the solid-state imaging device; and an analog signal is changed due to a method for connecting the solid-state imaging device and an external device together. A solid-state imaging device including an AD converter and configured to output a digital signal to outside has been recently proposed.
High-speed processing is particularly required for an AD converter embedded in a CMOS sensor. This is because, if the AD converter can perform processing at a high speed, the frame rate of an image output from the CMOS sensor can be increased. Of pixels arranged in a matrix, an AD converter is provided exclusively for pixels in the same column in order to realize the high-speed processing of the AD converter. In order to realize higher-speed processing of the AD converter, a clock frequency is increased. However, due to the response speed of a transistor and a line delay, there is an increase limit in clock frequency. In addition, the increase in crock frequency may result in an increase in power consumption of the AD converter.
In order to overcome the foregoing disadvantages, a technique described in Japanese Patent Publication No. 2004-304413 has been proposed. A conventional solid-state imaging device will be described with reference to FIG. 9.
FIG. 9 illustrates the conventional solid-state imaging device.
Referring to FIG. 9, an AD converter configured to convert high-order N bits and an AD converter configured to convert low-order M bits are used. Thus, AD conversion is performed at two levels. Specifically, after the high-order N bits are converted by a high-order AD converter, a difference (analog residual) between an analog value corresponding to a high-order N bit value and an analog value of signal voltage is input to a low-order AD converter. In such a manner, AD conversion of an entire digital value is performed.
A high accuracy is not required for conversion of high-order N bits. Thus, as a method for converting high-order N bits, a high-speed method with low linearity is employed. As a method for converting low-order M bits, a low-speed method with high linearity is employed. For example, in the case where N=3 and M=7, there are only 128 low-order M bit patterns. Thus, AD conversion is completed in 128 clocks. As a result, while an accuracy of 10 bits (=3+7) is ensured, the processing speed of AD conversion can be increased.